1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which lateral MOS transistors with a low breakdown voltage and lateral MOS transistors with a high breakdown voltage, both having a homopolar gate, and a vertical trench MOSFET are mounted together on a semiconductor substrate.
2. Description of the Related Art
In recent years, a wide variety of mobile devices have been distributed. As power sources for operating those mobile devices, Li-ion batteries have been heavily used, which have high energy density but generate no memory effect. Along therewith, a protection IC for detecting overcharge and overdischarge of the Li-ion battery has become essential. For example, a Li-ion battery for mobile phones has a battery voltage of about 3.6 V, but a voltage of 20 V or more may be applied during charging. Accordingly, it is required that the protection IC include an element having a high breakdown voltage.
In order that a CMOS transistor process can satisfy the specification of such a protection IC, it is necessary that the process can form a MOS transistor suitable for low voltage use and a MOS transistor suitable for high voltage use. This is because, in order to satisfy its specification, the high breakdown voltage element needs to have a certain element size. Then the final chip size increases when the entire IC is formed of high breakdown voltage elements, with the result that the IC has no cost-competitiveness, and it becomes difficult to satisfy the demand for market price. Accordingly, it is necessary to reduce the chip size by using high breakdown voltage elements only in circuit sections to which a high voltage is applied, and using low breakdown voltage elements in other circuit regions. Further, when a trench power MOSFET is embedded in the protection IC, it is demanded to further reduce the chip size and reduce the on-resistance of the power MOSFET.
In view of such demands, as a manufacturing process for a semiconductor device serving as the protection IC, it is necessary to establish a method of manufacturing a semiconductor device, which includes a low breakdown voltage process, a high breakdown voltage process, and a trench process in a mixed manner.
In the following, with reference to FIGS. 11A to 14B, simple description is given of a conventional method of manufacturing a semiconductor device in which lateral MOS transistors having a low breakdown voltage and a high breakdown voltage, each having a homopolar gate, and a vertical trench MOSFET, are mounted together. The manufacturing method relating to the following items (1) to (5) are not shown in the drawings, but the semiconductor device is first formed as described in the following items (1) to (5).    (1) A high concentration buried layer is formed in a trench forming region by an ion implantation method.    (2) A P-type epi-layer is formed on a base substrate made of a P-type semiconductor by an epitaxial method.    (3) Respective well layers of lateral MOS transistors of a low breakdown voltage element and a high breakdown voltage element, and a vertical trench MOSFET are formed by an ion implantation method.    (4) An element isolation region and an electric field relaxation region of the high breakdown voltage element are formed by a LOCOS method or a shallow trench method.    (5) A first low concentration region is formed in the electric field relaxation region of the high breakdown voltage element by an ion implantation method.
After that, the semiconductor device is formed as illustrated in FIGS. 11A to 14B. In this manner, there is formed a semiconductor device in which the lateral MOS transistors of a low breakdown voltage element 102 and a high breakdown voltage element 103 and a vertical trench MOSFET 101, each having a homopolar gate, are mounted together.    (a) In an N-type vertical MOS transistor 101 forming region on an N-type first well layer 302, a trench 310 is formed by performing anisotropic etching toward the inside of a P-type semiconductor substrate 203 to have a depth does not reach an N-type buried layer 301 (FIG. 11A).    (b) A first gate insulating film 311 is formed by thermal oxidation along a surface of the P-type semiconductor substrate 203 and a wall surface of the trench (FIG. 11B).    (c) A first polycrystalline silicon layer 312 doped with N-type ions is formed on the first gate insulating film 311 (FIG. 11C).    (d) The first polycrystalline silicon layer 312 is subjected to etching to form a gate electrode 312 inside the trench (FIG. 12A).    (e) A nitride film 313 is formed on the entire surface of the P-type semiconductor substrate 203. Then, a photoresist is formed in a region other than a region of the high breakdown voltage element by a photolithography method. With use of the photoresist as a mask, the nitride film 313 is etched and removed only in the region of the high breakdown voltage element, in which a gate insulating film thereof is to be formed. Then, a relatively-thick second gate insulating film 314 is formed by thermal oxidation (FIG. 12B).    (f) After the nitride film 313 is removed, on the entire surface of the P-type semiconductor substrate 203, a third gate insulating film 315 of the lateral MOS transistor for the low breakdown voltage element 102 is formed by thermal oxidation (FIG. 12C).    (g) A non-doped second polycrystalline silicon layer is formed on the second and third gate insulating films (314 and 315) and also on the trench gate electrode. Then, N-type high concentration impurities and P-type high concentration impurities are introduced by an ion implantation method with use of separate masks into the second polycrystalline silicon layer (316 and 317) for NMOS transistors and PMOS transistors of the low breakdown voltage element and the high breakdown voltage element (FIG. 13A).    (h) The second polycrystalline silicon layer is subjected to etching, and thus an N-type second gate electrode 316 and a P-type second gate electrode 317 of the lateral MOS transistors of the low breakdown voltage element and the high breakdown voltage element are formed (FIG. 13B).    (i) With use of the second gate electrode 316 in an N-type lateral MOS transistor formation region of the low breakdown voltage element 102 on a P-type second well layer 304 as a mask, N-type impurities are introduced in a self-aligning manner to form a second low concentration N-type impurity region 318. Further, with use of the second gate electrode 317 in a P-type lateral MOS transistor formation region of the low breakdown voltage element 102 on an N-type second well layer 305 as a mask, P-type impurities are introduced in a self-aligning manner to form a second low concentration P-type impurity region 319. After that, an oxide film is formed by a CVD method or the like, and then anisotropic etching is performed. Thus, an oxide film spacer 323 is formed on a side wall of each of the second gate electrodes 316 and 317 (FIG. 13C).    (j) In a region of the N-type lateral MOS transistor formation region of the low breakdown voltage element 102 on the P-type second well layer 304, the region being separated from the second gate electrode 316 thereof by a desired distance, and in a surface region of the N-type vertical MOS transistor formation region, the surface region being provided in contact with the trench 310, N-type high concentration impurities are introduced by an ion implantation method to form sources and drains 320 (FIG. 14A).    (k) Ina region of the P-type lateral MOS transistor formation region of the low breakdown voltage element 102 on the N-type second well layer 305, the region being separated from the gate electrode thereof by a desired distance, P-type high concentration impurities are introduced by an ion implantation method to form high concentration P-type source and drain 321 (FIG. 14B).
Finally, although not shown, an interlayer insulating film is formed, and a hole for electrode formation is opened in the interlayer insulating film. Then, an aluminum electrode is formed.
In the conventional method of manufacturing a semiconductor device in which lateral MOS transistors of the low breakdown voltage element and the high breakdown voltage element and the vertical trench MOSFET, which each have a homopolar gate, are mounted together illustrated in FIGS. 11A to 14B, in the step of FIG. 12A, polycrystalline silicon is deposited to form the gate electrode inside the trench, and the polycrystalline silicon other than that inside the trench is entirely etched. Due to the etching fluctuations at this time, the thickness of the gate electrode inside the trench varies. With this variation, even when the source is subsequently formed on the P-type substrate surface, the source may not reach the gate electrode end. Thus, there may arise a problem in that the vertical trench MOSFET does not satisfy its specification of the drive capability characteristics.